1. Field of the Invention
The present invention relates, in general, to a method for a shallow junction of a semiconductor device and, more particularly, to the use of a rapid thermal process in which a semiconductor substrate implanted with ions through a thin insulating film is thermally treated at a high temperature for a short time under the condition of elevating the temperature at a great speed, in forming a shallow source/drain junction region.
2. Description of the Prior Art
Usually, the ultra high integration of semiconductor devices requires a significant reduction in the area of source/drain region. Conventionally, the formation of source/drain junction is accomplished by a preamorphization process in which heavy ions, such as arsenic, silicon or germanium, are implanted before the implantation of p type dopants, such as boron and boronfluoride ions, to prevent the channeling of boron or by a subsequent thermal treatment at a low temperature for a short time.
In order to better understand the background of the invention, a description will be given of a conventional method for forming a shallow junction of semiconductor device, in conjunction with FIG. 1, below.
First, a N-well 43 is formed in the upper part of a semiconductor substrate 41, followed by the sequential formation of a field oxide film 45, a gate oxide film 47, a gate electrode 49 and an oxide film spacer 51 over the N-well 43. The structure thus formed over the semiconductor substrate 41 serves as a mask in an ion-implantation process to form a p.sup.+ source/drain junction region 53. The ions are injected through a residual oxide film or intentionally grown thin oxide film 59 which will be formed on the p.sup.+ source/drain junction region 53. With the aim of preventing the damage attributable to the channeling effect of the dopant which is boron, the ion implantation and the metal impurities introducible into the Si substrate upon the ion-implantation, the residual oxide film 59 is formed from a thermal oxide film which is used to protect the semiconductor substrate 41 from etching for the formation of the gate electrode or from the residue after the formation of the oxide film spacer 51.
Next, an interlayer insulating film 55 is deposited over a Low pressure CVD-tetraethylorthosilicate (hereinafter referred to as "LPCVD-TEOS"), followed by the deposition of a blanket of a planarization layer 57 over the interlayer insulating film 55. The planarization layer 57 is an insulating film superior in fluidity, such as borophosphosilicate glass (hereinafter referred to as "BPSG").
However, with this conventional method it is very difficult to form a shallow junction satisfying the design rule for very large scale integration, especially p+n junction, for the following reasons.
First, a low energy for BF.sub.2 ion implantation is required to form a shallow p+n junction. However, although it is possible for a commercially available high current ion implanter to perform ion implantation at 10 KeV or less, its ion beam current is too low to apply the implanter for the process.
Second, the reduction in the temperature and period in the subsequent thermal process to the ion implantation, which is to make the junction shallow, is advantageous in the aspect of the junctions depth but is limited because there is a critical condition for planarizing the interlayer insulating film, such as BPSG. In addition, such a reduction also reduces dopant activation and defect removal, giving rise to increasing sheet resistance and junction leakage current.
Particularly, it is difficult to prevent the diffusion of boron upon such BF.sub.2 ion implantation because the fluorine implanted together makes the semiconductor substrate amorphous, resulting in that after the thermal treatment for the planarization of conventional LPCVD-TEOS and BPSG, defects are widely distributed below the boundary between an initially amorphized region and a non-amorphized region. Further, the defects are highly apt to be in the depletion layer of the junction, which would increase junction leakage current.
Although not shown, other conventional methods can accomplish shallow junction by reducing the temperature and time in the subsequent thermal treatment. However, neither electrical activation of dopant nor removal of defect can be achieved by almost all of them, so that the junction leakage current is very large. Likely, the critical condition for planarizing the interlayer insulating film, such as BPSG, significantly limits the reduction of the temperature and time of the subsequent thermal treatment, restraining the formation of shallow junction.
Owing to the above-mentioned limitation, the semiconductor devices fabricated by the conventional methods are problematic in reliability and high integration.